A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art. At the best of our knowledge, no other CML D-Latch topologies are able to operate at such a low supply voltage. The triple-tail D-Latch, also known as low voltage CML D-Latch allows a minimum supply voltage of 0.8V in the same reference 40nm CMOS process.