This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art. At the best of our knowledge, no other CML D-Latch topologies are able to operate at such a low supply voltage. The triple-tail D-Latch, also known as low voltage CML D-Latch allows a minimum supply voltage of 0.8V in the same reference 40nm CMOS process.

A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering / Scotti, G.; Trifiletti, A.; Palumbo, G.. - (2019), pp. 233-236. (Intervento presentato al convegno 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 tenutosi a fra) [10.1109/ICECS.2018.8618015].

A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering

Scotti G.
;
Trifiletti A.;
2019

Abstract

This paper presents a novel topology to implement CML D-Latches in deeply scaled CMOS technologies under very low supply voltage requirements. The proposed modified Folded MCML D-Latch topology exploits a dynamic body bias approach to achieve a reduction of the threshold voltage of about 100mV thus allowing proper operation with a minimum supply voltage as low as 0.6V. Simulation results in a commercial 40nm CMOS process are provided to show the advantages of the proposed approach with respect to the state of the art. At the best of our knowledge, no other CML D-Latch topologies are able to operate at such a low supply voltage. The triple-tail D-Latch, also known as low voltage CML D-Latch allows a minimum supply voltage of 0.8V in the same reference 40nm CMOS process.
2019
25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
current mode; D-Latch; low voltage; MCML; nanometer CMOS
04 Pubblicazione in atti di convegno::04b Atto di convegno in volume
A novel 0.6V MCML D-latch topology exploiting dynamic body bias threshold lowering / Scotti, G.; Trifiletti, A.; Palumbo, G.. - (2019), pp. 233-236. (Intervento presentato al convegno 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 tenutosi a fra) [10.1109/ICECS.2018.8618015].
File allegati a questo prodotto
File Dimensione Formato  
Scotti_A-novel-0.6_2019.pdf

solo gestori archivio

Tipologia: Versione editoriale (versione pubblicata con il layout dell'editore)
Licenza: Tutti i diritti riservati (All rights reserved)
Dimensione 1.2 MB
Formato Adobe PDF
1.2 MB Adobe PDF   Contatta l'autore

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11573/1390725
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 7
  • ???jsp.display-item.citation.isi??? 4
social impact