The increasing amount of data to be processed coming from multiple sources, as in the case of sensor networks, and the need to cope with constraints of security and privacy, make necessary the use of computationally efficient techniques on simple and cheap hardware architectures often distributed in pervasive scenarios. Random Vector Functional-Link is a neural network model usually adopted for processing distributed big data, but no constraints have been considered so far to deal with limited hardware resources. This paper is focused on implementing a modified version of the Random Vector Functional-Link network with finite precision arithmetic, in order to make it suited to hardware architectures even based on a simple microcontroller. A genetic optimization is also proposed to ensure that the overall performance is comparable with standard software implementations. The numerical results prove the efficacy of the proposed approach.
Finite precision implementation of random vector functional-link networks / Rosato, Antonello; Altilio, Rosa; Panella, Massimo. - 2017:(2017), pp. 1-5. (Intervento presentato al convegno 2017 22nd International Conference on Digital Signal Processing, DSP 2017 tenutosi a Londra, Regno Unito) [10.1109/ICDSP.2017.8096056].
Finite precision implementation of random vector functional-link networks
Rosato, Antonello;Altilio, Rosa;Panella, Massimo
2017
Abstract
The increasing amount of data to be processed coming from multiple sources, as in the case of sensor networks, and the need to cope with constraints of security and privacy, make necessary the use of computationally efficient techniques on simple and cheap hardware architectures often distributed in pervasive scenarios. Random Vector Functional-Link is a neural network model usually adopted for processing distributed big data, but no constraints have been considered so far to deal with limited hardware resources. This paper is focused on implementing a modified version of the Random Vector Functional-Link network with finite precision arithmetic, in order to make it suited to hardware architectures even based on a simple microcontroller. A genetic optimization is also proposed to ensure that the overall performance is comparable with standard software implementations. The numerical results prove the efficacy of the proposed approach.File | Dimensione | Formato | |
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