Topologie e metodologie di progetto di blocchi di elaborazione analogica di precisione in tecnologia a canale corto

Topologies and design methodologies for high precision analog processing blocks in short-channel technologies. With the explosive growth of battery-powered portable devices, power reduction in integrated circuits has become a major problem. In many of these portable systems the signal is processed in the digital domain by limiting the role of the analog part to interface circuits between analogous physical quantities and digital processing. Having analog circuits operating at the same voltage as the digital ones means that I can integrate on the same chip front-end and digital processing functions without the need for additional interface circuits, reducing the overall cost of the system. Another reason that pushes to low supply voltages is given by technological considerations, for sub micrometric channel lengths the thickness of gate oxide becomes so slim that it has been forced to reduce the supply voltage to avoid effects like breakdown of the oxide of gate. With the reduction of the supply voltage there is a consequent reduction in the dynamic of the input signal. To maintain the same dynamic range with a lower power supply voltage, the thermal noise in the circuit must also be proportionally reduced. Therefore capacitors used in the circuit must be increased to lower the KT/C noise. Therefore, for operational amplifiers that have the task of driving larger loads and for high resolution applications, doing it becomes even more difficult. There is, however, a compromise between noise and energy consumption. Because of this strong compromise, under certain conditions, energy consumption will actually increase in proportion to the decrease in power supply [1]. Another aspect that poses a significant problem to the reduction of consumption is the fact that battery technology is currently progressing at a much slower pace than that of electronic circuits. Nowadays, many electronic systems work with the power supplied by batteries alone, in some cases this problem is the most critical feature of the device, just think of networks of wireless sensors or implantable devices in the human body. There are also many switched-capacitor applications that require fast signal transitions and certain performance in given times. If I use a class A amplifier it would always be on even in the times when it is not necessary, which leads to considerable consumption. In this context, a possible solution can be represented by class AB transconductance amplifiers (OTA), which have the advantage of consuming a small current in quiescent condition and providing a large peak current when a large signal is applied. This peculiarity can be exploited to achieve fast settling times with low average power consumption. In many applications, such as active filters, Sample and Hold Amplifiers (SHA), pipeline ADCs, the use of fully differential amplifiers is required to exploit the advantages offered by differential signals, such as doubled dynamic range compared with that provided by a given voltage generator, low sensitivity to common mode disturbances and even order harmonics suppression. Various ways of achieving class AB OTAs are proposed in the literature. In all fully differential type implementations, there is a need for auxiliary circuits for controlling common mode output voltage (CMFB). These additional circuits introduce into the project additional constraints and static power consumption compared to the basic topologies of class AB amplifiers. This line of research has driven me to focus on two main topics, closely related to the aforementioned issues: 1- Low-voltage and Very-low-voltage design of Class AB OTAs blocks for S/H; 2- Study of a behavioral modeling of Class AB OTAs; This work is divided into five chapters. Chapter 1 is an introduction to the state of the art of Class-AB OTAs. From the assessment of the state of the art there will emerge various ways to realize class-AB "OTAs" but only those that comply with certain constraints will be taken into consideration. The topologies chosen and on which the studies will be conducted will be those that will show the best performance in terms of power consumption, and that are implemented in according to the symmetrical current mirror OTAs. Chapter 2 is an introduction to figures of merit (FOMs) that will be used to characterize OTAs from a performance point of view. Also in chapter 2 the study and comparison of four topologies emerged from the state of the art evaluation will be conducted. These topologies will be compared from the point of view of consumption and performance of both small and large signal using the FOMs. From the comparison the one will be selected that has the best performances from the point of view of power consumption, bandwidth and large signal behavior. This topology that is preferred over the other choices will be shown to have a performance limit linked to the low value of the CMRR. Chapter 3 regards the improvement of the performance of the topology chosen to make it the most performing of the state of the art. Three possible methods will be proposed to increase the CMRR of the structure with little impact on consumption but without altering the low signal performance. The first two will be based on open loop techniques while the latter on a closed loop technique. Chapter 4 regards the design of other topologies with the aim of improving their performance. Chapter 5 regards behavioral modeling of a class AB OTA. Given that there are no guidelines in the literature on how to design class AB OTAs, a model will be proposed in this chapter, in its alpha phase, with the intent to understand how some parameters are linked to the settling time in similar way as to how is done for class A amplifier.