This paper presents a checkpointing-recovery scheme for Time Warp parallel simulation. The scheme relies on a checkpointing protocol, namely mixed state saving, embedding both sparse and incremental state saving modes, and on a state recovery procedure embedding both forward and backward recovery modes. This scheme is a generalization of many previous solutions, which can be obtained as particular instances of it by selecting appropriate values for the checkpointing protocol parameters. We also present two regulating algorithms to adaptively tune the checkpointing protocol parameters, in order to make the protocol reacting to variable rollback behavior. A synthetic benchmark in several different configurations has been used for evaluating and comparing our scheme with previous solutions. The obtained data show that our solution allows faster execution and, in addition, keeps quite low the amount of memory used for recording state information; this allows the scheme to not adversely affect performance when memory is a critical resource. © 2001 Elsevier Science B.V.
A checkpointing-recovery scheme for Time Warp parallel simulation / Vittorio, Cortellessa; Quaglia, Francesco. - In: PARALLEL COMPUTING. - ISSN 0167-8191. - 27:9(2001), pp. 1227-1252. [10.1016/s0167-8191(01)00081-3]
A checkpointing-recovery scheme for Time Warp parallel simulation
QUAGLIA, Francesco
2001
Abstract
This paper presents a checkpointing-recovery scheme for Time Warp parallel simulation. The scheme relies on a checkpointing protocol, namely mixed state saving, embedding both sparse and incremental state saving modes, and on a state recovery procedure embedding both forward and backward recovery modes. This scheme is a generalization of many previous solutions, which can be obtained as particular instances of it by selecting appropriate values for the checkpointing protocol parameters. We also present two regulating algorithms to adaptively tune the checkpointing protocol parameters, in order to make the protocol reacting to variable rollback behavior. A synthetic benchmark in several different configurations has been used for evaluating and comparing our scheme with previous solutions. The obtained data show that our solution allows faster execution and, in addition, keeps quite low the amount of memory used for recording state information; this allows the scheme to not adversely affect performance when memory is a critical resource. © 2001 Elsevier Science B.V.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.