The aim of the NA62 experiment is to measure the branching ratio of the decay K+ → π+νν to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from π+π0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is ∼100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence.
The NA62 LAV front-end electronics and the L0 trigger generating firmware / Antonelli, A.; Corradi, G.; Gonnella, F.; Kozhuharov, V.; Martellotti, S.; Moulson, M.; Raggi, M.; Spadaro, T.. - In: POS PROCEEDINGS OF SCIENCE. - ISSN 1824-8039. - 0:(2014). (Intervento presentato al convegno 3rd Technology and Instrumentation in Particle Physics Conference, TIPP 2014 tenutosi a Amsterdam; Netherlands).
The NA62 LAV front-end electronics and the L0 trigger generating firmware
Raggi, M.;
2014
Abstract
The aim of the NA62 experiment is to measure the branching ratio of the decay K+ → π+νν to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from π+π0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is ∼100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed. © Copyright owned by the author(s) under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike Licence.File | Dimensione | Formato | |
---|---|---|---|
Antonelli_NA62_2014.pdf
solo gestori archivio
Tipologia:
Versione editoriale (versione pubblicata con il layout dell'editore)
Licenza:
Creative commons
Dimensione
365.18 kB
Formato
Adobe PDF
|
365.18 kB | Adobe PDF | Contatta l'autore |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.