Nanostructured porous materials form Micro- and nano-electronics applications

This thesis work presents new research on porous silicon technologies for the heterogeneous integration on silicon platforms, as a key enabling technology for future 3D integrated systems. Porous silicon can be obtained with CMOS compatible processes on localized area on silicon wafer and, due to its tunable electrical, mechanical and thermal characteristics is an effective buffer material. Moreover, macroporous morphologies of porous silicon can can be exploited for the realization of “bed-of-nails” type through wafer interconnects, paving the way to high density, low-cost, through silicon vias. This work is divided in three parts: the first part introduces porous silicon, summarizes the available literature and presents process characterization for the porous layers obtained in this work and their properties; the second part describes the layer transfer technology and the buried cavities technologies developed in this work using the porous layers presented in the previous part; the last part introduces two applications of the layer transfer technology: compliant contacts and integrated physically small antennas.