Best Student Paper Award

Many industrial applications concerning pattern recognition techniques often demand to develop suited low cost embedded systems in charge of performing complex classification tasks in real time. To this aim it is possible to rely on FPGA for designing effective and low cost solutions. Among neurofuzzy classification models, Min-Max networks constitutes an interesting tool, especially when trained by constructive, robust and automatic algorithms, such as ARC and PARC. In this paper we propose a parallel implementation of a Min-Max classifier on FPGA, designed in order to find the best compromise between model latency and resources needed on the FPGA. We show that by rearranging the equations defining the adopted membership function for the hidden layer neurons, it is possible to substantially reduce the number of logic elements needed, without increasing the model latency, i.e. without any need to lower the classifier working frequency.