statistiche ricercatore

Nome	#
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks	89
Secure double rate registers as an RTL countermeasure against power analysis attacks	83
Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications	80
Security evaluation and optimization of the delay-based dual-rail pre-charge logic in presence of early evaluation of data	65
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations	47
Design techniques for secure cryptographic circuits in deep submicron technologies	42
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family	21
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher	17
Simulated power analysis attacks on a DDPL crypto-core without routing constraints	14
Totale	458

	Totale	Lug	Ago	Sett	Ott	Nov	Dic	Gen	Feb	Mar	Apr	Mag	Giu
2018/2019	53	0	0	0	0	0	0	0	0	0	0	27	26
2019/2020	103	17	4	0	3	10	14	12	13	13	5	10	2
2020/2021	65	4	7	7	2	2	0	1	3	8	26	5	0
2021/2022	77	0	5	7	4	8	1	0	6	18	6	4	18
2022/2023	65	18	9	0	4	4	4	2	4	3	5	6	6
2023/2024	43	1	8	3	3	4	8	0	6	0	6	4	0
Totale													458

Catalogo dei prodotti della ricerca