A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated.
DESIGN AND CHARACTERIZATION OF A STANDARD CELL SET FOR DELAY INSENSITIVE VLSI DESIGN / A., Degloria; Paolo, Faraboschi; Olivieri, Mauro. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. 2, ANALOG AND DIGITAL SIGNAL PROCESSING. - ISSN 1057-7130. - 41:6(1994), pp. 410-415. [10.1109/82.300201]
DESIGN AND CHARACTERIZATION OF A STANDARD CELL SET FOR DELAY INSENSITIVE VLSI DESIGN
OLIVIERI, Mauro
1994
Abstract
A working synthesis system for delay insensitive (DI) VLSI design is used as a case study to investigate the correspondence between theoretical formalization and electric circuit operation. Most of the previous research has treated DI VLSI design from a formal point of view. We illustrate the new features involved in the electrical design and characterization of DI cells, reporting circuit schematic and standard cell characterization results. Some integrated circuits built with the cells have been fabricated.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
