We propose an architecture for a bufferless packet optical switch employing the wavelength dimension for contention resolution. The optical packet switch is equipped with tunable wavelength converters shared among the input lines. An analytical model Is proposed in order to determine the number of converters needed to satisfy prefixed packet loss probability constraints. This analytical model very accurately fits with simulations results. A sensitivity analysis of the required number of converters as a function of the main system parameters (number of input and output lines, number of wavelengths, …) and traffic parameters has been carried out. Making use of the introduced dimensioning procedure we have observed that the proposed architecture allows a saving in terms of employed number of converters with respect to the other architectures proposed in literature. Such a saving can reach about 95% of the number of converters.
Packet loss in a bufferless optical WDM switch employing shared tunable wavelength converters / Eramo, Vincenzo; Listanti, Marco. - In: JOURNAL OF LIGHTWAVE TECHNOLOGY. - ISSN 0733-8724. - STAMPA. - 18:12(2000), pp. 1818-1833. [10.1109/50.908743]
Packet loss in a bufferless optical WDM switch employing shared tunable wavelength converters
ERAMO, Vincenzo;LISTANTI, Marco
2000
Abstract
We propose an architecture for a bufferless packet optical switch employing the wavelength dimension for contention resolution. The optical packet switch is equipped with tunable wavelength converters shared among the input lines. An analytical model Is proposed in order to determine the number of converters needed to satisfy prefixed packet loss probability constraints. This analytical model very accurately fits with simulations results. A sensitivity analysis of the required number of converters as a function of the main system parameters (number of input and output lines, number of wavelengths, …) and traffic parameters has been carried out. Making use of the introduced dimensioning procedure we have observed that the proposed architecture allows a saving in terms of employed number of converters with respect to the other architectures proposed in literature. Such a saving can reach about 95% of the number of converters.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.