A monolithic 2.5 Gb/s clock and data recovery circuit based on Silicon bipolar technology

A monolithic Clock and Data Recovery (CDR) circuit for SDH STM-16 (2.5 Gb/s) digital receivers has been designed and fabricated using Maxim GST-2 27 GHz Silicon bipolar technology. The main functions carried out by the IC are: signal amplification (40 dB) and limitation, clock recovery and decision. The design is intended to achieve a complete 2.5 Gb/s receiver by using the IC and a low noise preamplifier (transimpedance stage), mounted in a DIL package. The integrated circuit comprises about 400 active devices, used both for analog and digital blocks, and uses two supply voltages of 5 and -4.5 V. The input port is decoupled by external capacitors and matched to 50 Omega using on-chip resistors, whereas clock and data outputs are open collector type. The die size is 2 x 2 mm(2) and the chip has been packaged using a TQFP 48 pins plastic package. Measurements under 2(31)-1 PRBS data stream have shown an input sensitivity below 5 mVpp, rms output jitter below 7 ps and total power consumption of 0.8 W.