On border traps in back-side-illuminated CMOS image sensor oxides

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing E′ donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation.