Catalogo dei prodotti della ricerca

Sfoglia per Autore  

Opzioni
Mostrati risultati da 1 a 20 di 49
Titolo Data di pubblicazione Autore(i) File
Contributions in evaluating the statistical impact of technology variations on delay and power dissipation of logic cells 2010 Olivieri, Mauro; Menichelli, Francesco; Mastrandrea, Antonio; Nenzi, Paolo
A delay model allowing nano-CMOS standard cells statistical simulation at the logic level 2011 Mastrandrea, Antonio; Menichelli, Francesco; Olivieri, Mauro
A new logic level delay modeling paradigm for nano-CMOS standard cell variation-aware simulation 2012 Mastrandrea, Antonio; Olivieri, Mauro
Using safe operation regions to assess the error probability of logic circuits due to process variations 2013 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
A general design methodology for synchronous early-completion-prediction adders in Nano-CMOS DSP architectures 2013 Olivieri, Mauro; Mastrandrea, Antonio
Combined Impact of NBTI Aging and Process Variations on Noise Margins of Flip-Flops 2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Novel approaches to quantify failure probability due to process variations in nano-scale CMOS logic 2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Safe operation region characterization for quantifying the reliability of CMOS logic affected by process variations 2014 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs 2014 Abbas, Zia; Mastrandrea, Antonio; Olivieri, Mauro
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs 2014 Olivieri, Mauro; Mastrandrea, Antonio
Statistical characterization, analysis and modeling of speed performance in digital standard cell designs subject to process variations 2014 Mastrandrea, Antonio
Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops 2015 Khalid, Usman; Mastrandrea, Antonio; Olivieri, Mauro
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions 2015 Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro
Introducing approximate memory support in Linux Kernel 2017 Stazi, Giulia; Menichelli, Francesco; Mastrandrea, Antonio; Olivieri, Mauro
An emulator for approximate memory platforms based on QEmu 2017 Menichelli, Francesco; Stazi, Giulia; Mastrandrea, Antonio; Olivieri, Mauro
Investigation on the optimal pipeline organization in RISC-V multi-threaded soft processor cores 2017 Olivieri, Mauro; Cheikh, Abdallah; Cerutti, Gianmarco; Mastrandrea, Antonio; Menichelli, Francesco
Optimal pipeline stage balancing in the presence of large isolated interconnect delay 2017 Olivieri, Mauro; Menichelli, Francesco; Mastrandrea, Antonio
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique 2018 Abbas, Zia; Zahra, Andleeb; Olivieri, Mauro; Mastrandrea, Antonio
Impact of approximate memory data allocation on a H.264 software video encoder 2018 Stazi, G.; Adani, L.; Mastrandrea, A.; Olivieri, M.; Menichelli, F.
AppropinQuo: a platform emulator for exploring the approximate memory design space 2018 Stazi, G; Mastrandrea, A; Olivieri, M; Menichelli, F
Mostrati risultati da 1 a 20 di 49
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile