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Mostrati risultati da 1 a 14 di 14
Titolo Data di pubblicazione Autore(i) File
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits 1-gen-2011 Abbas, Zia; Vanni, Genua; Olivieri, Mauro
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology 1-gen-2011 Abbas, Zia; Scotti, Giuseppe; Olivieri, Mauro
Yield optimization for low power current controlled current conveyor 1-gen-2012 Abbas, Zia; M., Yakupov; Olivieri, Mauro; A., Ripp; G., Strobe
Sizing and optimization of low power process variation aware standard cells 1-gen-2013 ABBAS, ZIA; KHALID, USMAN; OLIVIERI, Mauro
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) 1-gen-2013 Abbas, Zia; Olivieri, Mauro; Marat, Yakupov; Andreas, Ripp
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells 1-gen-2014 Abbas, Zia; Olivieri, Mauro
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs 1-gen-2014 Abbas, Zia; Mastrandrea, Antonio; Olivieri, Mauro
Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell 1-gen-2015 Abbas, Zia; Olivieri, Mauro; Khalid, Usman; Ripp, Andreas; Pronath, Michael
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions 1-gen-2015 Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions 1-gen-2015 Khalid, Usman; Mastrandrea, Antonio; Abbas, Zia; Olivieri, Mauro
Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations 1-gen-2016 Abbas, Zia; Olivieri, Mauro; Ripp, Andreas
Optimal transistor sizing for maximum yield in variation-aware standard cell design 1-gen-2016 Abbas, Zia; Olivieri, Mauro
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique 1-gen-2018 Abbas, Zia; Zahra, Andleeb; Olivieri, Mauro; Mastrandrea, Antonio
LEADER: Leakage currents estimation technique for aging degradation aware 16 nm CMOS circuits 1-gen-2019 Abbas, Z.; Zahra, A.; Olivieri, M.
Mostrati risultati da 1 a 14 di 14
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